High quality uniform random number generation for massively parallel simulations in FPGAs

被引：0
|
作者：
Thomas, DB [1 ]
Luk, W [1 ]
机构：
[1] Univ London Imperial Coll Sci Technol & Med, Dept Comp, London SW7 2AZ, England
来源：
2005 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG 2005) | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper details the design and implementation of three uniform random number generators for use in. massively parallel simulations in FPGAs. The three different generators are tailored to make use of three different types of hardware resource: logic, RAM, and DSP blocks. This allows the random number generator to be fitted into resources left-over after the main application has been written. The three generators till pass the most stringent empirical statistical tests for randomness, and till have periods appropriate for long running simulations.
引用
收藏
页码：84 / 91
页数：8
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