Implementation of Block Adaptive Quantizer as a peripheral module for the FPGA-based SAR system

被引：3

作者：

Kniola, Michal ^{[1
]}

Kawalec, Adam ^{[1
]}

Lesnik, Czeslaw ^{[1
]}

Szugajew, Marcin ^{[1
]}

机构：

[1] Mil Univ Technol, Fac Elect, Inst Radioelect, Kaliskiego Str 2, PL-00908 Warsaw, Poland

来源：

2017 18TH INTERNATIONAL RADAR SYMPOSIUM (IRS) | 2017年

关键词：

D O I：

10.23919/IRS.2017.8008231

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Due to large quantity of data needed for image synthesis in SAR applications, methods of raw signal compression were developed alongside actual imaging systems. Although performance of modern processing units allows on-platform, online image synthesis, data compressor still can be a valuable addition. Since it is no longer necessary part of SAR system, it should be delivered in a flexible, easy to use and low cost form - like low-resources demanding Intellectual Property core. In this paper chosen properties of raw SAR signal and some of compression methods are presented followed by compressor IP core implementation results.

引用

页数：9

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