FPGA implementation of high-speed neural network for power amplifier behavioral modeling

被引:9
作者
Bahoura, Mohammed [1 ]
机构
[1] Univ Quebec, Dept Engn, Rimouski, PQ G5L 3A1, Canada
关键词
Adaptive modeling; Neural network; Power amplifier; Memory effects; Pipelining; FPGA; DIGITAL PREDISTORTER; HARDWARE;
D O I
10.1007/s10470-014-0263-7
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a high-speed pipelined architecture of dynamic neural network is proposed for power amplifier behavioral modeling. This architecture is implemented on field programmable gate array (FPGA) using Xilinx system generator and Virtex-6 FPGA ML605 Evaluation Kit. The novelty of the proposed architecture is that it provides higher operating frequency, lower output latency, and less required resources. These improvements are obtained by reducing the bit-width data and by efficiently redistributing the inserted pipelining delays. The new pipelined architecture is evaluated and compared to the conventional and pseudo-conventional ones in terms of the resource utilization, the maximum operating frequency, and the modeling performances using the 16-QAM modeled test signal. This architecture is verified using JTAG hardware co-simulation both for single step and free-running clock modes.
引用
收藏
页码:507 / 527
页数:21
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