A framework for run-time reconfigurable systems

被引:10
作者
Eisenring, M [1 ]
Platzner, M [1 ]
机构
[1] Swiss Fed Inst Technol, Comp Engn & Networks Lab, CH-8092 Zurich, Switzerland
关键词
multi-FPGA systems; run-time reconfiguration; design representation;
D O I
10.1023/A:1013627403946
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a framework for run-time reconfigurable systems. The framework provides a methodology and a design representation which allow to plug in different design and implementation tools. Front-end tools cover design capture, temporal partitioning and scheduling; back-end tools provide reconfiguration control, communication channel generation, estimation, and the final code composition. This paper elaborates on two of the framework's main issues: First, we discuss the design representation comprising aspects of the problem, the target architecture, and the communication channels. Second, we present a hierarchical approach to reconfiguration control in multi-FPGA systems.
引用
收藏
页码:145 / 159
页数:15
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