10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

被引：0

作者：

Tian, L ^{[1
]}

Wang, ZG ^{[1
]}

Chen, HT ^{[1
]}

Xie, TT ^{[1
]}

Lu, JH ^{[1
]}

Tao, R ^{[1
]}

Dong, Y ^{[1
]}

Xie, SZ ^{[1
]}

机构：

[1] SE Univ, Inst RF & OE ICs, Nanjing 210096, Peoples R China

来源：

FIBER OPTICS AND OPTOELECTRONICS FOR NETWORK APPLICATIONS | 2001年 / 4603卷

关键词：

SDH system; high-speed ICs; 1 : 4 demultiplexer; SCL; 0.25 mu m CMOS;

D O I：

10.1117/12.444544

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 1:4 demultiplexer in a standard 0.25 mum CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1mm(2) area. It consumes 693mW from a 3.3 V supply. The operating bit rates is higher than 10Gb/s.

引用

页码：121 / 124

页数：4