Ring Amplifiers for Switched Capacitor Circuits

被引:155
作者
Hershberg, Benjamin [1 ]
Weaver, Skyler [1 ]
Sobue, Kazuki [2 ]
Takeuchi, Seiji [3 ]
Hamashita, Koichi [3 ]
Moon, Un-Ku [1 ]
机构
[1] Oregon State Univ, Corvallis, OR 97331 USA
[2] AKM Technol Corp, Miyazaki 8800805, Japan
[3] Asahi Kasei Microdevices Corp, Atsugi, Kanagawa 2430021, Japan
关键词
A/D; ADC; analog to digital conversion; analog to digital converter; CLS; correlated level shifting; high resolution; low power; nanoscale CMOS; rail-to-rail; RAMP; ring amp; ring amplification; ring amplifier; ringamp; scalability; scaling; slew-based; split-CLS; stabilized ring oscillator; switched capacitor; CMOS AMPLIFIER; LOW-POWER; 10-BIT; OPAMP;
D O I
10.1109/JSSC.2012.2217865
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 mu m CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.
引用
收藏
页码:2928 / 2942
页数:15
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