Panel-Based Large-Scale RDL Interposer Fabricated Using 2-μm-Pitch Semi-Additive Process for Chiplet-Based Integration

被引：4

作者：

Kudo, Hiroshi ^{[1
]}

Takano, Takamasa ^{[1
]}

Tanaka, Masaya ^{[1
]}

Mawatari, Hiroshi ^{[1
]}

Kitayama, Daisuke ^{[1
]}

Tai, Takahiro ^{[1
]}

Tsunoda, Tsuyoshi ^{[1
]}

Kuramochi, Satoru ^{[1
]}

机构：

[1] Dai Nippon Printing DNP Co Ltd, 250-1 Wakashiba, Kashiwa, Chiba 2770871, Japan

来源：

IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022) | 2022年

关键词：

Heterogeneous; Chiplet; RDL interposer; Fan Out Wafer Level Package (FOWLP); Fan Out Panel Level Package (FOPLP); AIB; HBM; High Bandwidth; Si interposer;

D O I：

10.1109/ECTC51906.2022.00137

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A panel-based large-scale redistribution-layer (RDL) interposer has been fabricated using a 2-mu m-pitch semi-additive process. A key technology in the panel-based processing is dry plasma etching of the Cu-seed/barrier metal layers as it enables precise control of a very narrow trace width (1 mu m) while maintaining a high aspect ratio (greater than 3). This controllability was demonstrated by measuring the electrical resistance and electrical isolation of Cu traces. The patterned 2-mu m-pitch Cu traces were covered with inorganic dielectrics to increase their reliability. Focusing on the maximum signal transmission distance and energy efficiency of signal transmission, we compared the 2-mu m-pitch Cu traces with damascene-based Cu traces by using 3D electromagnetic field simulation. The fabricated large-scale RDL interposer, consisting of five conductive layers, is well suited for achieving high-speed processing in AI, graphics, and other high-performance computing systems.

引用

页码：836 / 844

页数：9

共 14 条

[1]

[Anonymous], SINGL CHIP MULT INT

[2]

[Anonymous], JESD235D

[3]

[Anonymous], High-Performance Computing in Off-the-Shelf DRAM Chips

[4] Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration [J].

Durgun, Ahmet C. ;

Qian, Zhiguo ;

Aygun, Kemal ;

Mahajan, Ravi ;

Hoang, Tim Tri ;

Shumarayev, Sergey Yuryevich .

2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2019, :667-673

[5]

Github, AIB SPECIFICATION

[6] High Bandwidth Memory Interface on Organic Substrate: Challenges to Electrical Design [J].

Heyfitch, Vadim ;

Dong, Shen ;

Na, Nanju ;

Shi, Hong ;

Gandhi, Jaspreet ;

Xi, Jane ;

Wu, Susan .

2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, :1289-1294

[7] Demonstration of Fine Pitch RDL in Fanout Panel Level Packaging [J].

Kim, Dowan ;

Park, Seokbong ;

Heo, Mina ;

Choi, Daeyeon ;

Jung, Hyunchul .

IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, :1070-1075

[8] High-speed, High-density, and Highly-manufacturable Cu-filled Through-Glass-Via Channel (Cu bridge) for Multi-chiplet Systems [J].

Kudo, Hiroshi ;

Takano, Takamasa ;

Akazawa, Miyuki ;

Yamada, Shouhei ;

Sakamoto, Kouji ;

Kitayama, Daisuke ;

Iida, Haruo ;

Tanaka, Masaya ;

Tai, Takahiro .

IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, :1031-1037

[9] Effectiveness of Inorganic Dielectric Layer on Submicron-scale Cu Traces against Thermal Oxidative Stress [J].

Kudo, Hiroshi ;

Takano, Takamasa ;

Sakamoto, Kouji ;

Kitayama, Daisuke ;

Iida, Haruo ;

Tanaka, Masaya ;

Tai, Takahiro ;

Okazaki, Yumi ;

Suzuki, Jyunya ;

Maekawa, Shinji .

IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, :353-358

[10]

Kudo H, 2017, IEEE CPMT SYMP JAP, P5, DOI 10.1109/ICSJ.2017.8240055

← 1 2 →