A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier

被引：41

作者：

Akter, Md Shakil ^{[1
]}

Makinwa, Kofi A. A. ^{[2
]}

Bult, Klaas ^{[2
]}

机构：

[1] Broadcom Netherlands BV, NL-3981 AJ Bunnik, Netherlands

[2] Delft Univ Technol, Dept Microelect, NL-2628 CD Delft, Netherlands

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2018年 / 53卷 / 04期

关键词：

Amplifier; analog linearization technique; analog-to-digital converter (ADC); capacitive degeneration; cross-coupled capacitors; digital nonlinearity calibration; dynamic residue amplifier; integrator; split-capacitor technique; PIPELINED ADC; RESIDUE AMPLIFICATION; DIGITAL CALIBRATION; DB SFDR; CMOS;

D O I：

10.1109/JSSC.2017.2778277

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV(pp, diff) and 4x gain, it achieves -100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 mu W at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26x compared with that of state-of-the-art high-linearity amplifiers.

引用

页码：1115 / 1126

页数：12

共 24 条

[1] A Low-Power Capacitive Charge Pump Based Pipelined ADC [J].

Ahmed, Imran ;

Mulder, Jan ;

Johns, David A. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (05) :1016-1027

[2]

Akter MS, 2015, PROC EUR SOLID-STATE, P315, DOI 10.1109/ESSCIRC.2015.7313890

[3] A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter [J].

Ali, Ahmed M. A. ;

Dillon, Christopher ;

Sneed, Robert ;

Morgan, Andrew S. ;

Bardsley, Scott ;

Komblum, John ;

Wu, Lu .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (08) :1846-1855

[4]

[Anonymous], 1992, NTC 92 NAT TEL C

[5] A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC [J].

Brooks, Lane ;

Lee, Hae-Seung .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (12) :3329-3343

[6]

Dolev Noam, 2013, 2013 Symposium on VLSI Circuits, pC98

[7]

Enz C. C., 1996, Emerging Technologies: Designing Low Power Digital Systems (Cat. No.96TH8189), P79, DOI 10.1109/ETLPDS.1996.508872

[8] A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration [J].

Grace, CR ;

Hurst, PJ ;

Lewis, SH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (05) :1038-1046

[9]

Hershberg B., 2012, 2012 IEEE International Solid-State Circuits Conference (ISSCC), P460, DOI 10.1109/ISSCC.2012.6177090

[10] A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier [J].

Hsu, CC ;

Wu, HT .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :263-266

← 1 2 3 →