A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

被引：44

作者：

Verbruggen, Bob ^{[1
,2
]}

Craninckx, Jan ^{[1
]}

Kuijk, Maarten ^{[2
]}

Wambacq, Piet ^{[1
,2
]}

Van der Plas, Geert ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

[2] Vrije Univ Brussel, Dept ETRO, Brussels, Belgium

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 03期

关键词：

Analog-digital conversion; calibration; CMOS analog integrated circuits; comparators;

D O I：

10.1109/JSSC.2009.2012449

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies, and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 U per conversion step and occupies 0.02 mm(2) in a 90 mn 1P9M digital CMOS process.

引用

页码：874 / 882

页数：9

共 22 条

[1]

Chen CY, 2008, SYMP VLSI CIRCUITS, P12, DOI 10.1109/VLSIC.2008.4585932

[2] A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS [J].

Chen, Shuo-Wei Michael ;

Brodersen, Robert W. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2669-2680

[3]

DALY DC, 2008, IEEE INT SOL STAT CI, P554

[4]

DRAXELMAYR D, 2004, IEEE ISSCC FEB

[5] 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC [J].

Ginsburg, Brian P. ;

Chandrakasan, Anantha P. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (04) :739-747

[6] A background comparator calibration technique for flash analog-to-digital converters [J].

Huang, CC ;

Wu, JT .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (09) :1732-1740

[7] A CURRENT-CONTROLLED LATCH SENSE AMPLIFIER AND A STATIC POWER-SAVING INPUT BUFFER FOR LOW-POWER ARCHITECTURE [J].

KOBAYASHI, T ;

NOGAMI, K ;

SHIROTORI, T ;

FUJIMOTO, Y .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) :523-527

[8] An embedded 0.8 V/480 μW 6B/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique [J].

Lin, J ;

Haroun, B .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (12) :1610-1617

[9] Efficient 6-bit A/D converter using a 1-bit folding front end [J].

Nagaraj, K ;

Chen, F ;

Le, T ;

Viswanathan, TR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (08) :1056-1062

[10] A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18μm CMOS with 5.8GHz ERBW [J].

Nuzzo, P. ;

Van der Plas, G. ;

De Bernardinis, F. ;

Van der Perre, L. ;

Gyselinckx, B. ;

Terreni, P. .

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, :873-+

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