Design of an active-inductor-based termination circuit for high-speed I/O

An active inductor termination for high-speed I/O circuits is presented. In comparison with the conventional active-inductor-based circuits, the proposed topology operates from a lower supply voltage and/or consumes less power. A prototype of the active termination with a CML output driver is designed, simulated, and laid out in a 90 nm CMOS process. The eye-opening and jitter performance in the eye-diagram simulations of the active termination compare favorably with its passive counterparts. In comparison with a passive-inductor-based design, the circuit consumes additional 1.327 mW DC power while occupying a die area of 17 pm x 25 pm, which is more than 60 times smaller than the area of a termination circuit with a 0.8 nH passive inductor.