Through-Silicon-Via (TSV) Filling by Electrodeposition of Cu with Pulse Current at Ultra-Short Duty Cycle

被引：55

作者：

Jin, Sanghyun ^{[1
]}

Wang, Geon ^{[1
]}

Yoo, Bongyoung ^{[1
]}

机构：

[1] Hanyang Univ, Dept Mat Engn, Ansan 426791, South Korea

来源：

JOURNAL OF THE ELECTROCHEMICAL SOCIETY | 2013年 / 160卷 / 12期

关键词：

COPPER; ELECTROMIGRATION; METALLIZATION; TECHNOLOGY; STACKING; SI;

D O I：

10.1149/2.050312jes

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Through-Si-via (TSV) filling with electrodeposited Cu was performed with a pulse current consisting of very a short duty cycle to achieve 3D interconnection in high density integrated circuit (IC) devices. Low frequency was unacceptable in this condition, because a highly acidic electrolyte attacked the seed layer and Cu deposit obtained with low current efficiency during comparably longer off time period. An increased frequency critically enhanced the filling rate of Cu, which was mainly related to the improvement of the current efficiency and lower dissolution rate. In pulse conditions, high density nanoscale twin structure and strain fields were observed, which were caused by induced stress during the on-time because of high peak current density. Application of pulse deposition reduced thermal extrusion of Cu that was related to the imperfect microstructure of the deposited Cu. (C) 2013 The Electrochemical Society. All rights reserved.

引用

页码：D3300 / D3305

页数：6

共 24 条

[11] Copper metallization reliability [J].

Lloyd, JR ;

Clemens, J ;

Snede, R .

MICROELECTRONICS RELIABILITY, 1999, 39 (11) :1595-1602

[12] Ultrahigh strength and high electrical conductivity in copper [J].

Lu, L ;

Shen, YF ;

Chen, XH ;

Qian, LH ;

Lu, K .

SCIENCE, 2004, 304 (5669) :422-426

[13] Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns [J].

Moffat, T. P. ;

Josell, D. .

JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2012, 159 (04) :D208-D216

[14] Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology [J].

Morrow, P. R. ;

Park, C. -M. ;

Ramanathan, S. ;

Kobrinsky, M. J. ;

Harmes, M. .

IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :335-337

[15] Electromigration: A review [J].

Pierce, DG ;

Brusius, PG .

MICROELECTRONICS RELIABILITY, 1997, 37 (07) :1053-1072

[16]

Ramm P., 2003, MAT RES SOC P, V766

[17] The development of a tapered silicon micro-micromachining process for 3D microsystems packaging [J].

Ranganathan, N. ;

Lee, D. Y. ;

Ebin, L. ;

Balasubramanian, N. ;

Prasad, K. ;

Pey, K. L. .

JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2008, 18 (11)

[18] Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique [J].

Ryu, Suk-Kyu ;

Jiang, Tengfei ;

Lu, Kuan H. ;

Im, Jay ;

Son, Ho-Young ;

Byun, Kwang-Yoo ;

Huang, Rui ;

Ho, Paul S. .

APPLIED PHYSICS LETTERS, 2012, 100 (04)

[19] Microstructure Effect on EM-Induced Degradations in Dual Inlaid Copper Interconnects [J].

Sukharev, Valeriy ;

Kteyan, Armen ;

Zschech, Ehrenfried ;

Nix, William D. .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2009, 9 (01) :87-97

[20] Mechanism of copper electrodeposition by pulse current and its relation to current efficiency [J].

Tsai, WC ;

Wan, CC ;

Wang, YY .

JOURNAL OF APPLIED ELECTROCHEMISTRY, 2002, 32 (12) :1371-1378

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