A Quasi-2D Threshold Voltage Model for Short-channel Junctionless (JL) Double-gate MOSFETs

被引：0
|
作者：
Chiang, Te-Kuang [1 ]
机构：
[1] Natl Univ Kaohsiung, Adv Devices Simulat Labotory, Dept Elect Engn, Kaohsiung, Taiwan
来源：
2012 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID STATE CIRCUIT (EDSSC) | 2012年
关键词：
bulk conduction mode; quasi-2D scaling theory; threshold voltage; junctionless(JL) double-gate MOSFETs;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Based on the bulk conduction mode of the quasi-2D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion (AM/IV) operation mode for junctionless/junction-based (JUJB) double-gate MOSFETs. The model is verified by the 2-D device simulator and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFEs due to its simple formula and computational efficiency.
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页数：4
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