A new fast locking charge pump PLL: analysis and design

被引：4

作者：

Sadeghi, Vahideh Sadat ^{[1
]}

Miar-Naimi, Hossein ^{[1
,2
]}

机构：

[1] Babol Univ Technol, Integrated Circuit Res Lab, Babol Sar, Iran

[2] Babol Univ Technol, Elect & Elect Engn Fac, Babol Sar, Iran

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2013年 / 74卷 / 03期

关键词：

Fast locking; CPPLL; Analysis; Design; BBFC;

D O I：

10.1007/s10470-012-0018-2

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a new structure for a fast locking charge pump phase locked loop (CPPLL) is introduced which overcomes the trade-off between the settling time and overshoot of the system. This fast locking PLL uses an auxiliary bang-bang frequency comparator (BBFC) as a lock-aid. An additional charge pump current controlled by the output of the BBFC is injected into the main loop filter capacitor to accelerate the locking process. An analytical approach to extract the differential equation governing on the system's dynamics is used to evaluate the performance of this fast locking PLL. A heuristic method that results in an approximate solution for the extracted differential equation is also proposed. The correctness of the presented differential equation and its closed-form solutions are verified by comparing the obtained closed-form solutions and simulation results. Using the obtained closed-form solutions, we predict the behavior of the system and design a fast BBFC-CPPLL which meets the system's requirements. Correctness of the differential equation and its closed-form solutions are verified by comparing the obtained closed-form solutions and simulation results.

引用

页码：569 / 575

页数：7

共 12 条

[1]

Armaroli D, 1996, 38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, P893, DOI 10.1109/MWSCAS.1995.510233

[2] An adaptive bandwidth phase locked loop with locking status indicator [J].

Choi, YS ;

Choi, HH ;

Kwon, TH .

Korus 2005, Proceedings, 2005, :826-829

[3]

Fouzar Y, 2000, ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, P252, DOI 10.1109/ICECS.2000.911531

[4]

Fouzar Y, 2000, ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II, P253, DOI 10.1109/ISCAS.2000.856309

[5] Fast Locking and High Accurate Current Matching Phase-Locked Loop [J].

Liu, Silin ;

Shi, Yin .

2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, :1136-1139

[6]

Razavi B., 2017, Design of Analog CMOS Integrated Circuits, V2nd

[7]

Sadeghi V. S., 2011, INT C EL ENG INF ICE, P1

[8]

Sadeghi VS, 2012, IEEE INT SYMP CIRC S, P1379

[9] Initial value problems for ODEs in problem solving environments [J].

Shampine, LF ;

Corless, RM .

JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS, 2000, 125 (1-2) :31-40

[10]

Valenta V, 2008, PROCEEDINGS OF THE 18TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA 2008, P127

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