Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique

被引:23
作者
Jain, Ankesh [1 ]
Venkatesan, Muthusubramaniam [1 ]
Pavan, Shanthi [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Madras 600036, Tamil Nadu, India
关键词
Analog-to-digital converter (ADC); continuous-time circuit; continuous-time integrator; delta-sigma; distortion reduction; high speed; linearity enhancement; loop filter; oversampling; quantizer; sigma delta; 130; nm; CMOS TRANSCEIVER; ADC; BANDWIDTH; DB;
D O I
10.1109/JSSC.2012.2191210
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We apply the "assisted opamp technique" to the design of a 1 GS/s single-bit continuous-time modulator (CTDSM) that achieves 10 bit resolution in 15.625 MHz bandwidth. The enhanced linearity and speed of the first integrator of the modulator, necessitated by single-bit operation, are obtained in a power efficient manner using opamp assistance. However, timing-skew between the feedback and assistant DAC currents can be a potential problem at high speeds. We analyze and give intuition for the effects of timing mismatch in such CTDSMs, and show that opamp assistance is quite robust to timing errors. Measurement results from an implementation in a 0.13 mCMOS process show that the modulator achieves a dynamic range of 67 dB in 15.625 MHz bandwidth while consuming 4 mW.
引用
收藏
页码:1615 / 1625
页数:11
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