A 64-bit fast adder with 0.18μm CMOS technology

Based on various CMOS technologies: 0.18 mu m, 0.151 mu m, 0.13 mu m and 90nm, the performance comparisons among three parallel prefix adders with different bit widths are made in this paper. And the adder architecture fit for deep submicron technology is selected according to the impact of connective wires on adder performance. The organization and circuit design of a 64-bit high speed binary parallel adder built in TSMC 2.5V 0.18 mu m 1P6M CMOS fabrication technology is presented. Using clock-delayed domino logic, the delay of each stage in the adder is reduced. The addition latency is no more than 668ps with about 4500 transistors integrated into the area of 0.13mm(2).