From design-for-test to design-for-debug-and-test: Analysis of requirements and limitations for 1149.1

被引:6
作者
Alves, GR [1 ]
Ferreira, JMM [1 ]
机构
[1] DEE, ISEP, P-4200 Porto, Portugal
来源
17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年
关键词
D O I
10.1109/VTEST.1999.766706
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging teals, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149. 1 test infrastructure.
引用
收藏
页码:473 / 480
页数:4
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