A Scalable DC/DC Converter with Fast Load Transient Response and Security Improvement

被引:1
|
作者
Liu, Xingye [1 ]
Ampadu, Paul [1 ]
机构
[1] Virginia Tech, Dept Elect & Comp Engn, Blacksburg, VA 24061 USA
关键词
DC/DC converter; load transient response; scalable; side-channel attack; correlation coefficient;
D O I
10.1109/SOCC56010.2022.9908087
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a scalable DC/DC converter for system-on-chip (SoC) applications, to improve load transient response and reduce side-channel information leakage. Implemented using modularized circuit blocks, the proposed power supply can be scaled simply by interleaving and/or parallelizing. Using 1V as input, three outputs (each ranging from 0.3V to 0.92V with load currents from 40mA to 1A) are provided. Based on 32nm CMOS technology post-layout and in-package air-core inductor models, peak efficiency for a single output can reach 88%. Maximum reference voltage tracking speed is 31.95 V/mu s and peak load step response is 53 mA/ns. There are no observable voltage spikes, droops or cross regulations at any outputs and this can be maintained for cases with different power ratings. Further, delay blocks and circuit sharing are employed to protect side-channel information. Under re-keying settings, the Pearson correlation coefficient between input and output can be lowered to 0.1 and the actual key induced power trace cannot be recognized. The signal-to-noise ratio (SNR) for correct key guess can also be reduced by 10 times to resist information leakage. Without output capacitors, the converter consumes 2.85 mm(2) chip area.
引用
收藏
页码:124 / 129
页数:6
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