Near-Threshold SRAM Design on 40-nm CMOS Technology for Low Power Design

In this paper, a near-threshold SRAM circuit designed in SMIC 40nm CMOS technology is proposed. Since near-threshold supply voltage will reduce the write noise margin (WNM), transient negative bit-line (T-NBL) voltage technology is adapted in this circuit to improve the writing ability and the stability. The T-NBL uses two capacitors to connect the right and the left bit-lines, so the voltage level can be controlled by a logic signal. Thus an ideal negative pulse will be generated to improve the WNM. A series of simulation results indicated that WNM and writing speed was improved by T-NBL technique. Simulation results shows that the proposed circuit can work around 0.5V supply voltage at most.