Reduced pull-in time of phase-locked loops with a novel nonlinear phase-frequency detector

被引:0
作者
Liu, Lechang [1 ]
Li, Binhong [1 ]
机构
[1] Shanghai Jiao Tong Univ, Dept Elect Engn, Shanghai 200030, Peoples R China
来源
2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5 | 2005年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel nonlinear phase-frequency detector (PFD) is presented to achieve a fast-switching phase-locked loop (PLL)-based frequency synthesizer. Compared with the conventional nonlinear PFD, the proposed topology can further reduce the PLL acquisition time while the loop stability remains unchanged. Moreover, the new topology can decrease the capacitance value and the charge-pump current to 1/k of a conventional one as the loop bandwidth increases k times, thus saving substantial chip area and power consumption.
引用
收藏
页码:3301 / 3304
页数:4
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