A Virtual Space Vector Modulation Technique for the Reduction of Common-Mode Voltages in Both Magnitude and Third-Order Component

被引:88
作者
Tian, Kai [1 ]
Wang, Jiacheng [2 ]
Wu, Bin [1 ]
Xu, Dewei [1 ]
Cheng, Zhongyuan [3 ]
Zargari, Navid Reza [3 ]
机构
[1] Ryerson Univ, Dept Elect & Comp Engn, Toronto, ON M5B 2K3, Canada
[2] Simon Fraser Univ, Sch Mechatron Syst Engn, Surrey, BC V3T 0A3, Canada
[3] Rockwell Automat Canada, Medium Voltage R&D Dept, Cambridge, ON N1R 5X1, Canada
关键词
Common mode voltage; space vector modulation; third-order harmonic component; virtual space vector; voltage source inverter; GROUND LEAKAGE CURRENT; INVERTER-DRIVEN MOTOR; MATRIX CONVERTER; 3-PHASE INVERTER; SHAFT VOLTAGE; SVM METHOD; PWM; IMPLEMENTATION; CURRENTS; SYSTEMS;
D O I
10.1109/TPEL.2015.2408812
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique.
引用
收藏
页码:839 / 848
页数:10
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