Towards Accelerating Generic Machine Learning Prediction Pipelines

被引:0
作者
Scolari, Alberto [1 ]
Lee, Yunseong [2 ]
Weimer, Markus [3 ]
Interlandi, Matteo [3 ]
机构
[1] Politecn Milan, Milan, Italy
[2] Seoul Natl Univ, Seoul, South Korea
[3] Microsoft, Redmond, WA USA
来源
2017 IEEE 35TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) | 2017年
关键词
Machine Learning; Model Scoring; Prediction Pipelines; FPGA;
D O I
10.1109/ICCD.2017.76
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Machine Learning models are often composed by sequences of transformations. While this design makes easy to decompose and accelerate single model components at training time, predictions requires low latency and high performance predictability whereby end-to-end runtime optimizations and acceleration is needed to meet such goals. This paper shed some light on the problem by using a production-like model, and showing how by redesigning model pipelines for efficient execution over CPUs and FPGAs performance improvements of several folds can be achieved.
引用
收藏
页码:431 / 434
页数:4
相关论文
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Crankshaw Daniel, 2017, CLIPPER LOW LATENCY
[3]  
Kara K., 2017, FPGA ACCELERATED DEN, P160
[4]  
Lin X., 2017, GLSVLSI 2017, P415
[5]  
Pedregosa F., 2011, JMLR, V12