Interface states in polymer thin-film transistors based on poly(3-hexylthiophene)

Metal-polymer-insulator-silicon (MPIS) structures based on poly(3-hexylthiophene) (P3HT) as an active semiconductor layer were fabricated on a highly doped n+ Si substrate with SiO2 or HfTiO as the insulating layer. The electrical characteristics of the MPIS structures have been investigated by means of capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. The dependence of the capacitance on frequency was clearly observed for the two samples, which is explained with a long-relaxation time for carriers in the bulk of the polymer semiconductor for the MPIS structure with SiO2 insulator and with charge trapping in defect states at the P3HT/HfTiO interface for the MPIS structure with HfTiO insulator. A conductance peak is absent at high test frequency, while the conductance peak is obvious at low test frequency due to a higher probability for capture and release of carriers by the interface states at low frequency. The interface-state density is estimated as 1.9 x 10(11) cm(-2) eV(-1) and 6.3 x 10(10) cm(-2) eV(-1) for the P3HT/HfTiO and P3HT/SiO2 interfaces, respectively by C-V and G-V measurements at a frequency of 10 kHz.