Design of a Compact Fractional-N PLL-based Frequency Synthesizer for Dual-band DBS Applications

被引:0
作者
Liu, Zhiqiang [1 ]
Xu, Jinping [1 ]
Liu, Gang [1 ]
Pan, Yunlong [1 ]
机构
[1] Southeast Univ, State Key Lab Millimeter Waves, Nanjing, Jiangsu, Peoples R China
来源
2017 PROGRESS IN ELECTROMAGNETICS RESEARCH SYMPOSIUM - SPRING (PIERS) | 2017年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A compact fractional-N PLL-based frequency synthesizer, that delivers both 9.75 GHz and 10.6 GHz LO signals for dual-band digital broadcast satellite (DBS) applications, is presented in this paper. It is implemented utilizing a fractional-N PLL packaged IC with integrated VCO in combination with a fourth-order active loop filter. The overall circuit performance is simulated with the help of ADI's PLL Design software. A compact and low cost bias tee with low noise coupling effect is optimized with lumped components to minimize the phase noise degradation of reference signal due to the DC-associated noise. The measured phase noises of the frequency synthesizer are below -108 dBc/Hz 100 kHz for both 9.75 GHz and 10.6 GHz output signals, which is around 13 dB better than the phase noise specification for LO in current commercially available DBS receivers.
引用
收藏
页码:3812 / 3815
页数:4
相关论文
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