A 0.7-to-1.1-GHz All-Digital Phase-Locked Loop With A New Phase Frequency Detector AND Controlled Oscillator With Body-Biasing

被引:0
作者
Shabaany, Mohammad Hassan [1 ]
Saneei, Mohsen [2 ]
机构
[1] Grad Univ Technol, Dept Elect & Comp Engn, Kerman, Iran
[2] Shahid Bahonar Univ, Dept Elect & Comp Engn, Kerman, Iran
来源
2012 16TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS) | 2012年
关键词
All digital phase lock loop (ADPLL); phase frequency detector; frequency synthesizer; digitally controlled oscillator;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A 0.7-to-1.1-GHz all-digital phase locked loop with a new phase frequency detector and controlled oscillator with body-biasing is presented. Digital-to-voltage converter is controlled the bulk voltage in proposed voltage controlled oscillator, which results high frequency resolution and low power consumption. A search algorithm is used to generates the digital code for the digital-to-voltage converter. This all-digital phase locked loop uses a new structure for the phase-frequency-detector, which ensures high accuracy at phase frequency detecting and increasing lock speed. The proposed design is evaluated in PTM 65nm. The power consumption of the proposed circuit at 900 MHz frequency is 4.8mW.
引用
收藏
页码:54 / 58
页数:5
相关论文
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