Considerations and Optimization of Measurement Accuracy of Capacitance in Nano-Scale CMOS Technology

被引：3

作者：

Cao, Si Han ^{[1
]}

Yu, Xiao Peng ^{[1
]}

Pan, Yun ^{[1
]}

Shi, Zheng ^{[1
]}

Hu, Chang Hui ^{[2
]}

机构：

[1] Zhejiang Univ, Inst VLSI Design, Hangzhou 310027, Peoples R China

[2] Marvell Semicond, Santa Clara, CA 95054 USA

来源：

NANOSCIENCE AND NANOTECHNOLOGY LETTERS | 2012年 / 4卷 / 09期

基金：

中国国家自然科学基金;

关键词：

Nano-Scale; CMOS; Capacitance Measurement; CBCM; Process Variation; Optimization;

D O I：

10.1166/nnl.2012.1408

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

In this letter, various factors which affect the measurement accuracy of capacitance in nano-scale CMOS technology are discussed. A charge based capacitance measurement (CBCM) test structure with optimized parameters is presented. It has a higher measurement accuracy and narrower range of error, which are demonstrated by the Monte Carlo simulation. The circuit is designed and simulated in a standard 65 nm CMOS technology and is able to work robustly against process variations with sub-femto-farad resolution.

引用

页码：924 / 929

页数：6

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