An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

被引：6

作者：

Oh, Hyunggoy ^{[1
]}

Han, Taewoo ^{[2
]}

Choi, Inhyuk ^{[1
]}

Kang, Sungho ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul, South Korea

[2] Samsung Elect, Dept SOC Design Team, Gyeonggi Do, South Korea

来源：

IEEE TRANSACTIONS ON COMPUTERS | 2017年 / 66卷 / 01期

基金：

新加坡国家研究基金会;

关键词：

Post-silicon debug; MISR compaction; trace buffer; debug time; COMPRESSION;

D O I：

10.1109/TC.2016.2561920

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

引用

页码：38 / 44

页数：7