CMOS Compatible Gate-All-Around Vertical Silicon-Nanowire MOSFETs

被引：5

作者：

Yang, B. ^{[1
]}

Buddharaju, K. D. ^{[1
]}

Teo, S. H. G. ^{[1
]}

Fu, J. ^{[1
]}

Singh, N. ^{[1
]}

Lo, G. Q. ^{[1
]}

Kwong, D. L. ^{[1
]}

机构：

[1] Agcy Sci Technol & Res, Inst Microelect, Singapore 117685, Singapore

来源：

ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2008年

关键词：

D O I：

10.1109/ESSDERC.2008.4681762

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present vertical Gate-All-Around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50:1) vertical nanowires with diameter down to similar to 20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. n- and p-MOS devices thus fabricated with gate length similar to 120 nm to 150 nm showed excellent transistor characteristics with large drive current per wire, high I-on /I-off ratio (similar to 10(7)), good subthreshold slope (similar to 80mV/ dec) and low DIBL (similar to 20mV/ V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

引用

页码：318 / 321

页数：4

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