Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder

被引：4

作者：

Hebbar, Abhishek R. ^{[1
]}

Srivastava, Piyush ^{[1
]}

Joshi, Vinod Kumar ^{[1
]}

机构：

[1] Manipal Acad Higher Educ, Dept Elect & Commun Engn, Manipal Inst Technol, Manipal 576104, Karnataka, India

来源：

8TH INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING & COMMUNICATIONS (ICACC-2018) | 2018年 / 143卷

关键词：

CSLA; Parallel prefix tree; Group PG logic; BEC; BK; LF; KS etc;

D O I：

10.1016/j.procs.2018.10.402

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent Kung (BK), Ladner Fischer (LF) and Kogge Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BECCSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 tm CMOS technology. (C) 2018 The Authors. Published by Elsevier B.V.

引用

页码：317 / 324

页数：8

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