Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

被引:213
作者
Kumar, MJ [1 ]
Chaudhry, A [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, New Delhi 110016, India
关键词
device scaling; insulated gate field effect transistors; short-channel effects (SCEs); silicon-on-insulator (SOI); MOSFET; threshold voltage; two-dimensional (2-D) modeling;
D O I
10.1109/TED.2004.823803
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.
引用
收藏
页码:569 / 574
页数:6
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