Optimization of finite interval CMA implementation for FPGA

被引:3
作者
Hermánek, A [1 ]
Schier, J [1 ]
Sucha, P [1 ]
Hanzálek, Z [1 ]
机构
[1] Acad Sci Czech Republ, Inst Informat Theory & Automat, Prague, Czech Republic
来源
2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS) | 2005年
关键词
D O I
10.1109/SIPS.2005.1579842
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using Integer Linear Programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.
引用
收藏
页码:75 / 80
页数:6
相关论文
共 11 条
[1]  
Fimmel D., 2001, International Journal of Foundations of Computer Science, V12, P697, DOI 10.1142/S0129054101000825
[2]   COMPUTATION OF PLANE UNITARY ROTATIONS TRANSFORMING A GENERAL MATRIX TO TRIANGULAR FORM [J].
GIVENS, W .
JOURNAL OF THE SOCIETY FOR INDUSTRIAL AND APPLIED MATHEMATICS, 1958, 6 (01) :26-50
[3]  
HANEN C, 1995, DAMATH DISCRETE APPL, V57
[4]  
HERMANEK A, 2004, P EUR SIGN PROC C WI, P2039
[5]  
MAKHORIN A, 2004, GLPK 4 4 GNU LINEAR
[6]  
Matousek R, 2002, LECT NOTES COMPUT SC, V2438, P627
[7]  
Regalia PA, 2002, INT CONF ACOUST SPEE, P2285
[8]   Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit [J].
Sucha, P ;
Pohl, Z ;
Hanzálek, Z .
RTAS 2004: 10TH IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM, PROCEEDINGS, 2004, :404-412
[9]  
SUCHA P, 2005, OPTIMIZATION ITERATI
[10]  
TOUZNI A, 1996, P EUR SIGN PROC C TR, P1227