Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

被引：0

作者：

Moon, Junho ^{[1
]}

Hwang, Sanghoon ^{[1
]}

Kim, Daeyoon ^{[1
]}

Kang, Heewon ^{[1
]}

Yeo, Seungjin ^{[1
]}

Lee, Doobock ^{[1
]}

Song, Minkyu ^{[1
]}

机构：

[1] Dongguk Univ, Semicond Sci Dept, Seoul, South Korea

来源：

2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2008年

关键词：

DAC; current steering; Alpha-Power Law; small area;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the Alpha-Power Law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockley's square model. In this paper, we describe a 6-b 100MSPS CMOS current steering Digital-to-Analog Converter (DAC) with the Alpha-Power Law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8V, 0.18 mu m, 1-poly, 5-metal CMOS technology. It occupies 0.52mm(2) of silicon area with 15.8mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.

引用

页码：29 / 32

页数：4