Performance Analysis of 1 Bit Full Adder Circuits for 45 nm Technology

In this paper, we are proposing a 1 bit full adder using multi-threshold complementary metal oxide semiconductor (MTCMOS) full adder. We have improved the figure of merit (Power Delay Product) of the proposed full adder and analyze it with other 12 different types of full adders. The simulation environment is cadence virtuoso in 45 nm technology using BSIM 4 model. Twelve different full adder cells, collected from the literature are evaluated and ranked using the framework, which ensures fair comparison basis. Apart from this we are using transistor sizing and critical path delay technique for the performance enhancement of all the full adders. In similarity with the existing full adder designs, the present proposed circuit was found to offer significant improvement in terms of power, speed and Power Delay Product (PDP).