Design and Implementation of different architectures of Montgomery modular multiplication

The Montgomery multiplication is the main block of modular exponentiation in cryptography. This paper discusses the three different architectures of Montgomery Multiplication and their performance is compared in terms and area and time optimization. The architectures are designed to improvise the area and reduce time. The designs are implemented in Verilog HDL and simulated using Synopsys VCS. They are also synthesized in Synopsys Design Compiler using 45nm libraries to get the cell area. The experimental results show that the time required for one Montgomery multiplication measured in terms of number of clock cycles is reduced by 1.5%, 1% and 3.5 % for the three different architectures discussed here over the previous implementations. It is achieved by minimizing the signals controlling the critical path of the design. Also there is a reduction in total cell area due to technology for the three designs presented in this paper.