High-level customization framework for application-specific NoC architectures

被引:2
作者
Anagnostopoulos, Iraklis [1 ]
Bartzas, Alexandros [1 ]
Filippopoulos, Iason [2 ]
Soudris, Dimitrios [1 ]
机构
[1] Natl Tech Univ Athens, Sch Elect & Comp Engn, Athens, Greece
[2] Norwegian Univ Sci & Technol, Dept Elect & Telecommun, N-7034 Trondheim, Norway
关键词
Network-on-Chip; Design methodology; Automation framework; Mapping; Priorities assignment; Buffer sizing; Regular and irregular topologies; DESIGN SPACE EXPLORATION; NETWORK; CHIP; CORE;
D O I
10.1007/s10617-013-9114-5
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5xhigher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network's power consumption by an average of 45 % for both regular and irregular NoC design flow.
引用
收藏
页码:339 / 361
页数:23
相关论文
共 42 条
  • [31] HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
    Abi-Karam, Stefan
    Sarkar, Rishov
    Seigler, Allison
    Lowe, Sean
    Wei, Zhigang
    Chen, Hanqiu
    Rao, Nanditha
    John, Lizy
    Arora, Aman
    Hao, Cong
    2024 ACM/IEEE 6TH SYMPOSIUM ON MACHINE LEARNING FOR CAD, MLCAD 2024, 2024,
  • [32] HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
    Abi-Karam, Stefan
    Sarkar, Rishov
    Seigler, Allison
    Lowe, Sean
    Wei, Zhigang
    Chen, Hanqiu
    Rao, Nanditha
    John, Lizy
    Arora, Aman
    Hao, Cong
    PROCEEDINGS OF THE 2024 ACM/IEEE INTERNATIONAL SYMPOSIUM ON MACHINE LEARNING FOR CAD, MLCAD 2024, 2024,
  • [33] ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models
    Mariani, Giovanni
    Palermo, Gianluca
    Zaccaria, Vittorio
    Silvano, Cristina
    PARALLEL COMPUTING, 2013, 39 (09) : 504 - 519
  • [34] C to D-Wave: A High-level C Compilation Framework for Quantum Annealers
    Hassan, Mohamed W.
    Pakin, Scott
    Feng, Wu-chun
    2019 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2019,
  • [35] Prerequisites for a high-level framework to design sustainable plants in the e-waste supply chain
    Barletta, Ilaria
    Johansson, Bjorn
    Reimers, Johanna
    Stahre, Johan
    Berlin, Cecilia
    22ND CIRP CONFERENCE ON LIFE CYCLE ENGINEERING, 2015, 29 : 633 - 638
  • [36] A GIS-based framework for high-level climate change risk assessment of critical infrastructure
    Hawchar, Lara
    Naughton, Owen
    Nolan, Paul
    Stewart, Mark G.
    Ryan, Paraic C.
    CLIMATE RISK MANAGEMENT, 2020, 29
  • [37] Automatic Mapping of Application to Coarse-Grained Reconfigurable Architecture based on High-Level Synthesis Techniques
    Lee, Ganghee
    Lee, Seokhyun
    Choi, Kiyoung
    ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 395 - 398
  • [38] Machine Learning to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration
    Wang, Zi
    Schafer, Benjamin Carrion
    PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020,
  • [39] Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework
    Butt, Shahzad Ahmad
    Mancini, Stephane
    Rousseau, Frederic
    Lavagno, Luciano
    JOURNAL OF ELECTRONIC IMAGING, 2014, 23 (05)
  • [40] High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration
    Powell, Adam
    Savvas-Bouganis, Christos
    Cheung, Peter Y. K.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2013, 59 (10) : 1144 - 1156