High-level customization framework for application-specific NoC architectures

被引:2
作者
Anagnostopoulos, Iraklis [1 ]
Bartzas, Alexandros [1 ]
Filippopoulos, Iason [2 ]
Soudris, Dimitrios [1 ]
机构
[1] Natl Tech Univ Athens, Sch Elect & Comp Engn, Athens, Greece
[2] Norwegian Univ Sci & Technol, Dept Elect & Telecommun, N-7034 Trondheim, Norway
关键词
Network-on-Chip; Design methodology; Automation framework; Mapping; Priorities assignment; Buffer sizing; Regular and irregular topologies; DESIGN SPACE EXPLORATION; NETWORK; CHIP; CORE;
D O I
10.1007/s10617-013-9114-5
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5xhigher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network's power consumption by an average of 45 % for both regular and irregular NoC design flow.
引用
收藏
页码:339 / 361
页数:23
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