Improved VLSI interconnect

Metal interconnect has become a major limiting factor in the growth of VLSI technology. A passive VLSI interconnect layout is proposed in which the current density is constant along its length. The result is a tapered track that has lower capacitance, hence lower power consumption, and improved high frequency performance. Simulations indicate that tapered tracks give delay reductions that permit operating frequencies up to 33% higher, and power savings of 42%, compared with equivalent rectangular tracks. Such interconnects will be of value in high speed clock nets where low skew and long paths are necessary.