A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques

被引:8
作者
Banerjee, Kunal [1 ]
Karfa, Chandan [2 ]
Sarkar, Dipankar [1 ]
Mandal, Chittaranjan [1 ]
机构
[1] Indian Inst Technol, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India
[2] Synopsys India Pvt Ltd, Bangalore 560016, Karnataka, India
来源
2012 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED 2012) | 2012年
关键词
code motion validation; equivalence checking; value propagation; finite state machines with datapath;
D O I
10.1109/ISED.2012.28
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel value propagation based equivalence checking method of finite state machines with datapath (FSMDs) is presented here for validation of code motion transformations commonly applied during scheduling phase of high-level synthesis. Unlike many other reported techniques, our method is able to handle code motions across loop bodies. This is accomplished by repeated propagation of the mismatched values to subsequent paths until the values match or the final path segments are traversed without finding a match. Checking loop invariance of the values being propagated beyond the loops has been underlined to play an important role. The proposed method is capable of handling control structure modification as well. The method has been implemented and satisfactorily tested for some benchmark examples.
引用
收藏
页码:67 / 71
页数:5
相关论文
共 16 条
  • [1] PATH-BASED SCHEDULING FOR SYNTHESIS
    CAMPOSANO, R
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (01) : 85 - 93
  • [2] Chi-Hui Lee, 2011, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, P497, DOI 10.1109/ASPDAC.2011.5722241
  • [3] dos Santos L. C. V., 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), P296, DOI 10.1109/DAC.1999.781329
  • [4] Floyd R.W., 1967, P S APPL MATH, V19, P19, DOI DOI 10.1090/PSAPM/019/0235771
  • [5] Using global code motions to improve the quality of results for high-level synthesis
    Gupta, S
    Savoiu, N
    Dutt, N
    Gupta, R
    Nicolau, A
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (02) : 302 - 312
  • [6] SPARK: A high-level synthesis framework for applying parallelizing compiler transformations
    Gupta, S
    Dutt, N
    Gupta, R
    Nicolau, A
    [J]. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 461 - 466
  • [7] An equivalence-checking method for scheduling verification in high-level synthesis
    Karfa, Chandan
    Sarkar, Dipankar
    Mandal, Chittaranjan
    Kumar, Pramod
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (03) : 556 - 569
  • [8] Formal Verification of Code Motion Techniques Using Data-Flow-Driven Equivalence Checking
    Karfa, Chandan
    Mandal, Chittaranjan
    Sarkar, Dipankar
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2012, 17 (03)
  • [9] Kim Y, 2004, ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, P110
  • [10] Kim Y., 2008, P 18 ACM GREAT LAK S, P95