A comment on "Improving a nonenumerative method to estimate path delay fault coverage"

被引：0
|
作者：
Pomeranz, I [1 ]
Reddy, SM [1 ]
机构：
[1] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1999年 / 18卷 / 05期
关键词：
fault simulation; path delay faults;
D O I：
10.1109/43.759083
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A method to estimate the coverage of path delay faults obtained by a given test set, without enumerating paths is described. The number of detected faults was estimated by using new lines. A similar method that considers the tuple of lines instead of single lines is compared with the previous method. The nonenumerative path delay fault simulator of the method is based on increasing the accuracy of the fault coverage estimate obtained from the zero-order approximation by considering tuples of lines instead of single lines.
引用
收藏
页码：665 / 666
页数：2
相关论文
共 50 条
  • [41] Path delay fault testability analysis
    Sosnowski, J
    Wabia, T
    Bech, T
    IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 338 - 346
  • [42] Remote path delay fault simulation
    Gjermundnes, O
    Aas, EJ
    DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2005, : 428 - 434
  • [43] Exact delay fault coverage in sequential logic under any delay fault model
    Kumar, Mahilchi Milir Vaseekar
    Tragoudas, Spyros
    Chakravarty, Sreejit
    Jayabharathi, Rathish
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (12) : 2954 - 2964
  • [44] Delay Fault Coverage Increasing in Digital Circuits
    Siebert, Miroslav
    Gramatova, Elena
    16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), 2013, : 475 - 478
  • [45] A Method on Improving Fault Coverage of Semiconductor Test Patterns using a Distance Function
    Lee S.
    Lee S.
    Ahn J.-H.
    Transactions of the Korean Institute of Electrical Engineers, 2024, 73 (01): : 186 - 191
  • [46] USING FUNCTIONAL FAULT SIMULATION AND THE DIFFERENCE FAULT MODEL TO ESTIMATE IMPLEMENTATION FAULT COVERAGE
    SILBERMAN, GM
    SPILLINGER, I
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1990, 9 (12) : 1335 - 1343
  • [47] FSimGEO: A test generation method for path delay fault test using fault simulation and genetic optimization
    Sun, YH
    Wu, QF
    14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 225 - 229
  • [48] Transition path delay faults: A new path delay fault model for small and large delay defects
    Pomeranz, Irith
    Reddy, Sudhakar M.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (01) : 98 - 107
  • [49] Improving gate level fault coverage by RTL fault grading
    Mao, WW
    Gulati, RK
    INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 150 - 159
  • [50] A flexible path selection procedure for path delay fault testing
    Pomeranz, I
    Reddy, SM
    17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 152 - 159
12345