Construction of Coverage Data for Post-Silicon Validation Using Big Data Techniques

Full-system FPGA prototyping is now being widely used in the industry for System-on-Chip (SoC) verification. Prototyping platforms run tests in a fraction of time compared to traditional simulation based verification. However, unlike simulation, they do not provide a good visibility about the Design under Verification (DUV) or its achieved verification results. Coverage is the standard measure of validation effectiveness and is extensively used pre-silicon. But it is very challengeable to analyze coverage data in post-silicon validation. This usually requires the addition of extra logic to the silicon as coverage monitors, which are costly in terms of area, power and timing. In this paper, we propose a framework for coverage data construction from the HW design trace buffer values during silicon execution. Our approach avoids the addition of extra synthesized coverage monitors logic. Additionally, it overcomes the challenge of processing huge traces result from the execution of tests that are impossibly expensive to run in pre-silicon simulation. Our work applies state-of-the-art big data techniques to reduce the processing and coverage data construction overhead. Our results indicate how the proposed framework managed to extract coverage data from FPGA prototyping runs that matches the one generated from the pre-silicon verification results for new-to-verify HW designs.