Enabling sub-blocks Erase management to boost the performance of 3D NAND flash memory

被引：16

作者：

Chen, Tseng-Yi ^{[1
]}

Chang, Yuan-Hao ^{[1
]}

Ho, Chien-Chung ^{[2
]}

Chen, Shuo-Han ^{[3
]}

机构：

[1] Acad Sinica, Inst Informat Sci, Taipei, Taiwan

[2] Natl Taiwan Univ, Dept Comp Sci & Informat Engn, Taipei, Taiwan

[3] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu, Taiwan

来源：

2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2016年

关键词：

NAND flash; sub-block erased; garbage collection; FTL;

D O I：

10.1145/2897937.2898018

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

3D NAND has been proposed to provide a large capacity storage with low-cost consideration due to its high density memory architecture. However, 3D NAND needs to consume enormous time for garbage collection because of live-page copying overhead and long block erase time. To alleviate the impact of live-page copying on the performance of 3D NAND, a sub-block erase design has been designed. With sub-block erase design, this paper proposes a performance booster strategy to extremely boost the performance of garbage collection. As experimental results shows, the proposed strategy has a significant improvement on the average response time.

引用

页数：6

共 15 条

[1]

[Anonymous], PROCEEDINGS OF THE 1995 USENIX TECHNICAL CONFERENCE

[2]

Chen FH, 2015, DES AUT TEST EUROPE, P1209

[3]

Cheng SW, 2014, ICCAD-IEEE ACM INT, P734, DOI 10.1109/ICCAD.2014.7001433

[4]

Chiang ML, 1999, SOFTWARE PRACT EXPER, V29, P267, DOI 10.1002/(SICI)1097-024X(199903)29:3<267::AID-SPE233>3.0.CO

[5]

2-T

[6]

d'Abreu M. A., PARTIAL BLOCK ERASE

[7]

Katcher Jeffrey, 1997, TECHNICAL REPORT

[8]

Lee Y. k., ERASING METHOD NONVO

[9] iADRs: towards online adverse drug reaction analysis [J].

Lin, Wen-Yang ;

Li, He-Yi ;

Du, Jhih-Wei ;

Feng, Wen-Yu ;

Lo, Chiao-Feng ;

Soo, Von-Wun .

SPRINGERPLUS, 2012, 1 :1-16

[10] Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems [J].

Liu, Duo ;

Wang, Tianzheng ;

Wang, Yi ;

Shao, Zili ;

Zhuge, Qingfeng ;

Sha, Edwin H-M .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (10) :1450-1462

← 1 2 →