Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I (D) ), ON-state to OFF-state current ratio (I (ON) /I (OFF) ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G (m) R (O) ), output conductance (G (D) ), transconductance/drain current ratio (G (m) /I (D) ) and unity gain cut-off frequency (f (T) ). The effects of varying the spacer dielectric constant (k (sp) ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W (sp) ) on device performance are also studied. ON-state current marginally decreases with spacer width.