Multiplier evolution:: A family of multiplier VLSI implementations

This paper provides an overview of four floating point multiplier implementations spanning microprocessor designs from 1992 to the present. The algorithm of each multiplier is explored in detail, and key measures of area, delay and design complexity are compared. The approaches span from a simple linear array to a full tree-based network, each targeted at efficient very-large-scale integration implementation. The designs show a progression of implementation techniques encompassing a 20x increase in multiplier performance during this time period.