Ternary multiplication circuits using 4-input adder cells and carry look-ahead

被引：2

作者：

Herrfeld, A ^{[1
]}

Hentschke, S ^{[1
]}

机构：

[1] Univ Gesamthsch Kassel, Inst Periphere Mikroelekt, D-34109 Kassel, Germany

来源：

1999 29TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/ISMVL.1999.779713

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multipliers. Timing diagrams will be given for the binary and the ternary case with an optimal order of the adder inputs. Finally, we present a ternary carry look-ahead circuit for a further reduction of total time delay.

引用

页码：174 / 179

页数：6

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