Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs

被引：34

作者：

Hallstedt, J. ^{[1
]}

Hellstrom, P. -E. ^{[1
]}

Radamson, H. H. ^{[1
]}

机构：

[1] KTH Royal Inst Technol, Sch Informat & Commun Technol, S-16640 Kista, Sweden

来源：

THIN SOLID FILMS | 2008年 / 517卷 / 01期

关键词：

MOSFET; Gate length; Lithography;

D O I：

10.1016/j.tsf.2008.08.134

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Today MOSFET devices are approaching gate lengths on the order of 10 nm. This sets extreme demands on gate patterning technique. This paper describes a side wall transfer lithography technique to pattern decananomeer MOSFETs or nanowires. A correlated line edge roughness leading to a very low line width roughness was demonstrated for the patterned gates. Moreover, the technology was shown to be robust and reproducible with high yield and uniformity suitable for mass fabrication. Finally, integration of the sidewall transfer lithography was performed in various novel MOSFET devices. (C) 2008 Elsevier B.V. All rights reserved.

引用

页码：117 / 120

页数：4

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