High resolution ADC using phase modulation - Demodulation architecture

We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional Ii-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s, By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (in effective bits) was competitive with the best semiconductor high-resolution ADCs.