High-κ Gate Dielectrices for Nanoscale CMOS Devices: Status, Challenges, and Future

被引：7

作者：

Park, Dae-Gyu ^{[1
]}

Wang, Xinlin ^{[2
]}

机构：

[1] IBM TJ Watson Res Ctr, 1101 Kitchawan Rd,Route 134,PO 218, Yorktown Hts, NY 10598 USA

[2] IBM Corp, Semicond R&D Ctr, Div Microelect, Hopewell Jct, NY 12533 USA

来源：

DIELECTRICS FOR NANOSYSTEMS 4: MATERIALS SCIENCE, PROCESSING, RELIABILITY, AND MANUFACTURING | 2010年 / 28卷 / 02期

关键词：

BORON PENETRATION; METAL; TECHNOLOGY;

D O I：

10.1149/1.3372562

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

This paper describes historical efforts of replacing SiO2 by high-k dielectric, and an implementation of high-k/metal gate (HK/MG) gate stack into the product level of industry standard low power bulk technology and high performance silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) devices. HK/MG stack provides further device scaling in channel length and inversion thickness (T-inv), leading to enable contact gate pitch scaling. Mobility degradation with T-inv scaling and threshold voltage (V-t) variability due to random telegraph noise and random dopant fluctuations at 15nm node and beyond are discussed, followed by outlook of future generation CMOS devices.

引用

页码：39 / +

页数：2

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