System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs

被引：13

作者：

Chang, Kyungwook ^{[1
]}

Das, Shidhartha ^{[2
]}

Sinha, Saurabh ^{[3
]}

Cline, Brian ^{[3
]}

Yeric, Greg ^{[3
]}

Lim, Sung Kyu ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

[2] ARM Ltd, Cambridge CB1 9NJ, England

[3] ARM Inc, Austin, TX 78735 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2019年 / 27卷 / 04期

关键词：

Frequency- and time-domain analysis; monolithic 3-D (M3D) IC; power delivery network (PDN); power delivery network optimization; static and dynamic rail analysis;

D O I：

10.1109/TVLSI.2019.2897589

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As 2-D scaling reaches its limit, monolithic 3-D (M3D) IC is a leading contender for continuing equivalent scaling. Although M3D shows power and performance benefits over 2-D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive (Ldi/dt) components of power supply integrity. In addition, we present frequency- and time-domain analyses of M3D PDNs. We show that the additional resistance in M3D PDNs, while being worse for resistive drops, improves resiliency against ac current noise showing 35.9% peak impedance reduction compared to 2-D PDNs during worst case resonant oscillations. Then, we present methodologies to improve power supply integrity of M3D designs based on the observations. Our optimization methodologies offer up to 32.6% and 17.0% static and dynamic voltage drop reduction compared to the baseline M3D designs, respectively, showing 9.0% lower dynamic voltage drop compared to the 2-D counterparts.

引用

页码：888 / 898

页数：11

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