A Programmable Delay-Locked Loop Based Clock Multiplier

被引：0

作者：

Lee, Sungken ^{[1
]}

Park, Geontae ^{[1
]}

Kim, Hyungtak ^{[2
]}

Kim, Jongsun ^{[1
]}

机构：

[1] Hongik Univ, Elect & Elect Engn, Integrated Circuits & Syst Lab, 72-1 Sangsu Dong, Seoul 121791, South Korea

[2] Hongik Univ, Elect & Elect Engn, Microelect Reliabil Lab, Seoul 121791, South Korea

来源：

2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2012年

关键词：

GENERATION; DLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a programmable delay-locked loop (DLL) based clock multiplier that provides flexible integer clock multiplication for high-performance clocking applications. The proposed DLL-based clock multiplier removes harmonic lock and stuck problems, which allows changing of the input clock frequency and multiplication factor during operation without any external reset. The output frequency range is from 195 MHz to 1.0 GHz with a multiplication factor N = 4, 5, 8, 10, 16, and 20. The proposed clock multiplier, implemented in a 0.18-mu m 1.8-V CMOS process, occupies an active area of only 0.14 mm(2). This clock multiplier achieves a measured rms and peak-to-peak jitter of 7.11ps and 30.0ps at 1.0 GHz, respectively.

引用

页码：128 / 130

页数：3

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