H.264/AVC Hardware Encoders and Low-Power Features

被引：0

作者：

Nguyen, Ngoc-Mai ^{[1
]}

Beigne, Edith ^{[1
]}

Lesecq, Suzanne ^{[1
]}

Duy-Hieu Bui ^{[2
]}

Nam-Khanh Dang ^{[2
]}

Xuan-Tu Tran ^{[2
]}

机构：

[1] CEA Grenoble, LETI, F-38054 Grenoble, France

[2] VNU Univ Engn & Technol, Hanoi, Vietnam

来源：

2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2014年

关键词：

H.264; encoder; HW architecture; power feature; ARCHITECTURE DESIGN;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Because of significant bit rate reduction in comparison to the previous video compression standards, the H.264/AVC has been successfully used in a wide range of applications. In hardware design for H.264/AVC video encoders, power reduction is currently a tremendous challenge. This paper presents a survey of different H.264/AVC hardware encoders focusing on power features and power reduction techniques to be applied. A new H.264/AVC hardware encoder, named VENGME, is proposed. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized The actual total power consumption, estimated at RTL level, is 19.1m W.

引用

页码：77 / 80

页数：4

共 19 条

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