A logic nanotechnology featuring strained-silicon

被引：404

作者：

Thompson, SE ^{[1
]}

Armstrong, M ^{[1
]}

Auth, C ^{[1
]}

Cea, S ^{[1
]}

Chau, R ^{[1
]}

Glass, G ^{[1
]}

Hoffman, T ^{[1
]}

Klaus, J ^{[1
]}

Ma, ZY ^{[1
]}

Mcintyre, B ^{[1
]}

Murthy, A ^{[1
]}

Obradovic, B ^{[1
]}

Shifren, L ^{[1
]}

Sivakumar, S ^{[1
]}

Tyagi, S ^{[1
]}

Ghani, T ^{[1
]}

Mistry, K ^{[1
]}

Bohr, M ^{[1
]}

El-Mansy, Y ^{[1
]}

机构：

[1] Intel Corp, Logic Technol Dev, Hillsboro, OR 97006 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2004年 / 25卷 / 04期

关键词：

CMOS; metal-oxide-semiconductor field-effect transistors (MOSFET); strained-silicon (Si);

D O I：

10.1109/LED.2004.825195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology [1]. Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si1-xGex in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSEFT. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work, 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

引用

页码：191 / 193

页数：3

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